1. Field of the Invention
The present invention relates generally to digital data transmission and, more specifically, is directed to the correction of errors in digital audio signals.
2. Description of the Prior Art
It is known to use a cross-interleave technique for transforming a digital data signal into an error correctable code structure. A known construction suitable to perform such cross-interleave error correction is shown in FIG. 1 in which each of W.sub.0,W.sub.1,W.sub.2 and W.sub.3 represents an audio data series. When four words contained in the respective audio data series are applied to modulo 2 adders, each represented schematically in FIG. 1 by an open circle, a first parity data series P is generated. This data series P is fed to several delay circuits, each of which provides a different time delay represented by d,2d,3d,4d and 5d, where d represents one unit of delay time. The result of applying the first parity data series P to the several delay circuits providing different amounts of time delay is to rearrange the data series W.sub.0 to W.sub.3 from the first arrangement state into a second arrangement state. The five words derived from the data series in this second arrangement state are then added, in a second set of modulo 2 adders each indicated schematically in FIG. 1 by an open circle, thereby generating a second parity data series Q.
Because such cross-interleave technique has the feature that each word of a digital audio signal is contained in two parity data series P and Q, this technique has high error correcting capabilities. Nevertheless, in using this cross-interleave error correction coding method, when there are four erroneous words in one block, the probability that error correction is impossible must be considered. For example, in using a cross-interleave technique where four words of digital data are added with two parity words, a parity series formed thereby can be represented as in FIG. 2, in which each solid circle schematically represents one word of a code symbol. In FIG. 2, five words in the vertical direction represent a parity series P, and six words in the diagonal direction represent a parity series Q. Specific words symbolized by S.sub.0 through S.sub.5 are represented schematically by open circles having solid circular centers.
Assuming that the data transmission is random, and further assuming that, in a decoder, P-decoding and Q-decoding will be accomplished by using the parity P and the parity Q, respectively, and that such P- and Q-decoding will be alternately repeated a number of times, the extent to which error correction for each of the specific words S.sub.0 to S.sub.5 is impossible may be seen. For example, in the case of the word represented by symbol S.sub.0, when four symbols including the symbol S.sub.0 are arranged in a trapezoidal relationship on the data field, as represented in FIG. 2, and contain errors at the same time, two error words will be contained in the P- and Q-parity series, respectively, and, hence, such errors cannot be corrected. If the number of such trapezoidal patterns is counted, the probability that the error correction will not be possible can be determined. In regard to the words represented by the other symbols S.sub.1 to S.sub.5, when four words including these symbols are arranged to form a parallelogram and are simultaneously erroneous, the error correction is again seen to be impossible when using the cross-interleave technique.
If the probability that one word is erroneous is taken as P.sub.s, then the probability that the error correction will be impossible at each word represented by the symbols S.sub.0 to S.sub.5 is given as follows:
P.sub.0 =10 P.sub.s.sup.4 PA2 P.sub.1 =10 P.sub.s.sup.4 PA2 P.sub.2 =13 P.sub.s.sup.4 PA2 P.sub.3 =14 P.sub.s.sup.4 PA2 P.sub.4 =13 P.sub.s.sup.4 PA2 P.sub.5 =10 P.sub.s.sup.4
Of course, the case where more than five words are simultaneously erroneous can occur and, in that case, the error correction will also be impossible. However, the probability in such situation, which is less than P.sub.s.sup.5, is neglected. Not being limited to four words, generally in the case of n words-two parity, a similar tendency is apparent.
In such known error correcting coding method, the probability that error correction is impossible is dependent upon the data channel under consideration so that parity data is allocated to the position of S.sub.0,S.sub.1 or S.sub.5 where such probability is shown to be relatively low. Nevertheless, since information data is much more important than parity data used for error correction, it is desirable that information data, which may be pulse code modulation (PCM) data in the case of audio signals, be located at a position where the probability that the error correction is impossible becomes quite low, that is, it should be at a location where it can be assumed that most errors can be corrected.
FIG. 3 shows a relationship among various data points, and in which audio data series W.sub.0 and W.sub.1 are located at positions corresponding to symbols S.sub.0 and S.sub.1, respectively; parity data series Q and P are located at positions corresponding to symbols S.sub.2 and S.sub.3, respectively; and audio data series W.sub.2 and W.sub.3 are located at positions corresponding to symbols S.sub.4 and S.sub.5, respectively. In FIG. 3, five words represented by solid circles generate a parity word P, while six words represented by open circles generate a parity word Q. As may be seen in FIG. 3, in the series generating the parity word P, there is a blank appearing at the location corresponding to the parity word Q, and this blank poses a problem in the case of a complete cross-interleave error correcting technique.
In such complete cross-interleave technique, interleaving is completed with a unit formed of a predetermined number of words of PCM data. FIG. 4 illustrates a situation similar to that described above in which there are four symbols and two parity words, and data is written in a memory having a matrix structure of four symbols by m blocks. As shown in FIG. 4, four words represented by solid circles are read out to form a parity word P, which is written in the memory, and then five words represented by open circles are read out to form a parity word Q. The generation of the parity word P is completed in a matrix of four symbols by m blocks, and the generation of the parity word Q is completed in a matrix of five symbols by m blocks. A synchronizing signal, a block address signal, and a cyclic redundancy check (CRC) code for error detection are added to every block and then recorded.
In this kind of complete cross-interleave error correction, it is desirable that a large distance D (or number of blocks) exist between two words contained in a series for generating a parity symbol P, because the length of a burst error that is correctable by the parity symbol P is defined by this distance D (or number of blocks). Furthermore, it is necessary that the number of remaining blocks, represented by the distance D' in FIG. 4, be less than the number of blocks represented by the distance D. The distance D is the distance or number of blocks between the two closest words which are contained in the series for generating the parity P. As will be clear from FIG. 4, if the parity symbol Q is positioned at the center of one block, the distance between words W.sub.1 and P becomes 2D thereby presenting a problem in that the distance D or number of blocks between two symbols cannot be increased.
In view of the foregoing problem, a complete cross-interleave system has been proposed, for example, as described in detail in U.S. Pat. No. 4,562,578 having the same Assignee as this application, and in which one parity symbol P is positioned at the center of a block, where the probability is high that, if an error occurs there, it will be impossible to correct, while the other parity symbol Q is positioned at the end of the block in order to lengthen the block and thereby to maximize the burst error length that can be corrected.
The system disclosed in U.S. Pat. No. 4,562,578 is applied to a situation in which a stereophonic audio signal, related to a video signal of an NTSC system, is digitized and recorded on a magnetic tape by a rotary head in a manner now generally well-known.
FIG. 5 shows the arrangement of one data unit in which one word consists of eight bits, specifically, n=8 words, m=132 blocks, and n.times.m=1056 words. The digital audio signal of one field in the NTSC system is 1050 words, so that, when the sampling frequency is 2F.sub.h (where F.sub.h is the horizontal frequency), six words of control data (ID.sub.0, . . . ID.sub.5) must be added to the words in the field, preferably at the beginning thereof. In other words, six words of control data are added to the digital audio signal in one field, which is sequential as follows: L.sub.0,R.sub.0,L.sub.1,R.sub.1,R.sub.2, . . . L.sub.522, L.sub.523 and R.sub.523.
In such control data, ID.sub.0 is a marker word and ID.sub.1 to ID.sub.4 are time codes, in which ID.sub.1 represents hours, ID.sub.2 represents minutes, ID.sub.3 represents seconds, and ID.sub.4 represents fields. Word ID.sub.5 includes eight bits a.sub.0 to a.sub.7, which comprise the following information: bit a.sub.0 represents whether the control data is effective: bits a.sub.1 and a.sub.2 represent the specific kind of digital audio signal (monaural, stereo, bilingual, etc.); bit a.sub.3 discriminates between audio information and information for some other display and relates to one channel; bit a.sub.4 provides similar discrimination in relation to the other channel; bits a.sub.5 and a.sub.6 represent start and stop information and these bits are set to a high level at the start and stop of the recording; and bit a.sub.7 represents information related to avoiding damping.
The 1056 words that include the control data ID.sub.0 to ID.sub.5 are arranged so that they have a distance of 44 blocks in the lateral direction at every two words, that is, two-by-two, such as, ID.sub.0 -ID.sub.1,ID.sub.2 -ID.sub.3,ID.sub.4 -ID.sub.5, and so on. In a hardware implementation, this may be achieved by writing at addresses separated by 44 blocks, as controlled by the address control of a random access memory (RAM). If the control data or parity data are separated, then two words Li and Ri are arranged in the lateral direction or left to right direction in relation to FIG. 5. The reason the digital audio signal is interleaved by being divided into three in the lateral direction is that the correctable burst error length is thereby maximized, when using, for example, a mean-value interpolation. More particularly, by such alteral arrangement of Li and Ri, the correctable length can be made longer as compared with the case where they are arranged in the longitudinal direction or the up and down direction in FIG. 5.
Two parities, either odd or even, are added to the digital audio signal of one field that includes the control data. Referring now to FIG. 6, if the audio data series in each row of the above matrix structure is taken as W.sub.0,W.sub.1, . . . W.sub.7, a first parity series P having eight words in each data series is formed with a distance between such words of 14 blocks or 15 blocks in the lateral direction, and the words contained in this parity series P are symbolized by solid circles on FIG. 6.
If it were possible, all distances between two adjacent symbols of the first parity series P would be selected as fourteen blocks. However, since the distance D' at one portion may be as long as twenty blocks, then six blocks must be taken therefrom and used to form a distance of fifteen blocks between adjacent symbols at six different positions, thereby further enhancing the burst error correcting capability. Moreover, nine words, each of which is taken from the audio data series W.sub.0 to W.sub.7 and the parity series P, form a second parity series Q with a distance of twelve blocks between adjacent symbols, and the words contained in the series Q are symbolized by open circles in FIG. 6. The distance, in numbers of blocks, between the elements of the two parity series is chosen to be divisible by two or three. The first parity series P is positioned at the center of one block, while the second parity series Q is positioned at the end of the block. In other words, as described hereinabove, since the probability is high that errors occurring in data at the center of the block will be impossible to correct, U.S. Pat. No. 4,562,578 teaches to locate the parity series P at the center of the block, since it is less important than audio data, and further teaches to locate the parity series Q at the end of the block in order to maximize the distance between successive words that form the parity series P.
Each of the 132 blocks includes eight words of digital audio signal data, two words of parity data, and a cyclic redundancy check (CRC) code for error detection which may involve 16 bits added to the data of each block. A block synchronizing signal and a block address signal are also added to the group of blocks before it is recorded on a magnetic tape. If data of the first block is taken out of context and examined separately, it will appear as shown in FIG. 7, it being understood that after this block there will follow the second block, the third block, . . . up to the l32d 132D block, moving left to right in FIG. 5.
A digital data transmission system of the type disclosed in U.S. Pat. No. 4,562,578 is shown in FIG. 8, in which solid line arrows show the direction of signal flow during transmitting or recording, and broken line arrows show the direction of signal flow during receiving, playback or reproduction. More particularly, in the recording or transmitting mode of the system shown on FIG. 8, an audio signal to be recorded or transmitted is supplied through an input terminal 1 to an analog-to-digital converter (A/D)2, and the resulting digitized audio signal is written into either a random access memory (RAM) 3 or a random access memory (RAM) 4. Each of the random access memories 3 and 4 has sufficient capacity to contain the entire digital audio signal comprising one field. During the time that the audio input data is being written into one or the other of random access memories 3 and 4, the data of the previous field is being read out from the other random access memory 4 or 3, and is fed to a P,Q encoder/decoder 6, which generates two parities to be written back into the other RAM. The data are written into predetermined areas of RAMs 3 and 4, respectively, as shown in FIGS. 5 and 6, and, in order to read out this data in an interleaved state, an address generator 5 is provided to generate a predetermined block address, for example, by means of an address counter, a read only memory and an adder (not shown).
The digital audio signal and parity data that have been read out from either the RAM 3 or 4 are fed to an adder 7, where they are added with a block address produced by a block address generator 8. The combined output signals from adder 7 are fed to a parallel-to-serial converter 9, with the resultant serialized signal being fed to a CRC encoder/decoder 10. In this example, the CRC encoder/decoder 10 has a generation polynomial given by x.sup.16 +x.sup.12 +x.sup.5 +1 and generates a CRC code (CRCC) of 16 bits that is added to each block. The operation of CRC encoder/decoder 10 is controlled by timing signals from a CRC timing generator 11. Since frequency modulation (FM) is employed in the signals of this example, the output signal from CRC encoder/decoder 10 is fed to an FM encoder/decoder 12, and the output signal from FM encoder/decoder 12 is fed to an adder 13, in which it is added with a block synchronizing signal produced by a synchronizing signal generator 14. The combined signal from adder 13 is fed to a output terminal 15 from which it is recorded on a magnetic tape using a known rotary magnetic head recording apparatus or otherwise transmitted.
In the receiving or reproducing mode of the system shown on FIG. 8, a digital signal reproduced from a magnetic tape (not shown) is fed through an input terminal 16 to a synchronous detecting circuit 17, and the resulting detected signal is fed to FM encoder/decoder 12 where the signal is FM demodulated. The FM demodulated signal is fed to CRC encoder/decoder 10 where it is error checked by a CRC code at every block, with the result of this error checking being a one bit error pointer, which is memorized in pointer random access memories (RAMs) 18 and 19. The pointer RAMs 18 and 19 correspond to RAMs 3 and 4 and each error pointer is written at the respective address of their 1320 blocks (10.times.132=1320), and the block addresses common to RAMs 3 and 4 are also supplied to the pointer RAMs 18 and 9 from address generating circuit 5.
The reproduced and demodulated data signal is also supplied to a buffer 20 whose buffered output signal is fed to serial-to-parallel converter 21, which provides parallel-arranged data in a proper form for writing into RAMs 3 and 4. Buffer 20 functions to delay the reproduced data until an error pointer, which is the result of the CRC error check conducted by the CRC encoder/decoder 10, has been generated. In this reproducing mode, RAMs 3 and 4 operate in a fashion similar to that described above for the recording mode, so that, when one RAM 3 or 4 has one field of reproduced data being written therein, errors in reproduced data read out from the other RAM 4 or 3 are corrected. Upon writing reproduced data in either the RAM 3 or 4, an error word indicated by an error pointer is not written. To accomplish this, each error pointer read out from pointer RAM 18 or 19 is fed to a RAM timing generator 22, which generates control signals fed to RAMs 3 and 4 to prevent the writing of error words therein.
The reproduced data read out from RAMs 3 or 4 is supplied to P,Q encoder/decoder 6 to carry out error correction using known parity techniques and, once any errors in the data have been corrected, the data is again written back into RAM 3 or 4. In the case of such error correction, all that is required is that an error word have sufficient information to show that the word is erroneous and, as described above, the erroneous word itself is not written into RAM 3 or 4. If more than two error words are contained in one parity generating series, then error correction is impossible. However, when error correction using parity series P and error correction using parity series Q are alternately and repetitively carried out, the number of words for which error correction is impossible is reduced substantially.
The reproduced data read out from RAM 3 or 4 after errors have been corrected is supplied to an amending or interpolating circuit 23 that perform a mean-value-interpolating process on words having errors that cannot be corrected. The output of amending circuit 23 is fed to a digital-to-analog converter 24, and the analog output signal therefrom is fed through an output terminal 25 as a reproduced audio signal.
In the above-described error correction system, an error pointer is established for a data block including erroneous data on the basis of the corresponding CRC code. The error detection capability with CRC code is almost perfect in relation to, for example, a burst error of less than 16 bits, or a random error of less than 3 bits. However, there is a possibility of misdetection of errors which extend over numbers of bits greater than the above-mentioned magnitudes. For example, no error pointer may be established as to a data block including a burst error of more than 16 bits or a random error of more than 3 bits. If such misdetection is not compensated, scratch noises may arise in the reproduced audio. In addition, if correction is carried out on the basis of such misdetection, it results in miscorrection so that the error is further expanded.
It might be assumed that the above problem could be solved by using the Q parity series or P parity series to effect a parity check before effecting error correction. However, in such a parity check, when there is no error in a parity series, it is checked whether or not the syndrome of the parity series becomes zero. Therefore, if an error pointer is correctly established as to a parity series and the latter includes another error for which no error pointer is established, a parity check to the latter error is impossible. In that case, the erroneous data for which no error pointer is established cannot be corrected and remains erroneous.